On 24-01-23 19:36:17, Konrad Dybcio wrote:
>
>
> On 1/23/24 12:01, Abel Vesa wrote:
> > Add the required nodes to support display on X1E80100.
> >
> > Co-developed-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
> > Signed-off-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
> > Co-developed-by: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx>
> > Signed-off-by: Rajendra Nayak <quic_rjendra@xxxxxxxxxxx>
> > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 518 +++++++++++++++++++++++++++++++++
> > 1 file changed, 518 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > index e8d2ea2b26ed..247ff7a9e405 100644
> > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> > @@ -4,6 +4,7 @@
> > */
> > #include <dt-bindings/clock/qcom,rpmh.h>
> > +#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
> > #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
> > #include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
> > #include <dt-bindings/dma/qcom-gpi.h>
> > @@ -3298,6 +3299,523 @@ usb_1_ss1_role_switch: endpoint {
> > };
> > };
> > + mdss: display-subsystem@ae00000 {
> > + compatible = "qcom,x1e80100-mdss";
> > + reg = <0 0x0ae00000 0 0x1000>;
> > + reg-names = "mdss";
> > +
> > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_DISP_AHB_CLK>,
> > + <&gcc GCC_DISP_HF_AXI_CLK>,
> > + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> > +
> > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
> > +
> > + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
> > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
> > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> > + interconnect-names = "mdp0-mem",
> > + "mdp1-mem";
>
> You likely also want to add the cpu-cfg path
>
> [...]
>
> > +
> > + dispcc: clock-controller@af00000 {
> > + compatible = "qcom,x1e80100-dispcc";
> > + reg = <0 0x0af00000 0 0x20000>;
> > + clocks = <&bi_tcxo_div2>,
> > + <&bi_tcxo_ao_div2>,
> > + <&gcc GCC_DISP_AHB_CLK>,
>
> This clock is not actually registered with the CCF.. Which means it's
> also never cleanly shut down.. Please fix the clock driver and check
> which others got omitted as well.
>
Right, so this clock is actually enabled on probe and is expected to be
always-on.
And I just noticed that at least on SM8[456]50 it's the same.
So I guess the solution here is to drop it from the dt node and fix the
dt schema. For all these platforms.
> > + <&sleep_clk>,
> > + <0>, /* dsi0 */
> > + <0>,
> > + <0>, /* dsi1 */
> > + <0>,
> > + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */
> > + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> > + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
> > + <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> > + <&mdss_dp2_phy 0>, /* dp2 */
> > + <&mdss_dp2_phy 1>,
> > + <&mdss_dp3_phy 0>, /* dp3 */
> > + <&mdss_dp3_phy 1>;
> > + power-domains = <&rpmhpd RPMHPD_MMCX>;
>
> Likely:
>
> required-opps = <&rpmhpd_opp_low_svs>;
>
> so that the PLLs have a chance to spin up
>
> Konrad
