On 1/24/24 08:36, Manivannan Sadhasivam wrote:
PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is only required by the PCIe controller. Hence drop it from pcie_phy nodes. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> ---
So, I have a small phytest module that basically does this: phy_get phy_init phy_set_mode_ext(PCIE_RC) phy_power_on To load it, I skip PCIe init (comment out the node), then wait for clk and pmdomain unused cleanup, then load the phytest module to ensure that I'm not piggybacking off of the RC's resources. I tried it out on the CRD, on PCIE2A (NVMe) Without this patch, the PHY seems to init fine With this patch, I get: (1) qcom-qmp-pcie-phy 1c24000.phy: phy initialization timed-out Kicking the PCIe GDSC from the PHY, I additionally get: (2) gcc_pcie_2a_cfg_ahb_clk status stuck at 'off' I think we expected (2), but is (1) okay? Konrad
