PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy nodes.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index e78c83a897c2..23a9060f21d9 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -1571,12 +1571,11 @@ pcie0: pcie@1c00000 {
pcie0_phy: phy@1c06000 {
compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy";
reg = <0 0x01c06000 0 0x2000>;
- clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
- <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_EN>,
<&gcc GCC_PCIE0_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_0_PIPE_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
+ clock-names = "cfg_ahb", "ref", "rchng", "pipe";
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
reset-names = "phy";
@@ -1654,12 +1653,11 @@ pcie1: pcie@1c08000 {
pcie1_phy: phy@1c0e000 {
compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy";
reg = <0 0x01c0e000 0 0x2000>;
- clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
- <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ clocks = <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_1_CLKREF_EN>,
<&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe";
+ clock-names = "cfg_ahb", "ref", "rchng", "pipe";
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
reset-names = "phy";
--
2.25.1
