On 9/7/2023 1:06 PM, Konrad Dybcio wrote:
On 7.09.2023 07:55, Jagadeesh Kona wrote:
On 9/4/2023 9:32 PM, Konrad Dybcio wrote:
On 4.09.2023 11:27, Jagadeesh Kona wrote:
On 9/2/2023 5:33 PM, Konrad Dybcio wrote:
On 28.08.2023 08:48, Jagadeesh Kona wrote:
On 8/26/2023 4:17 PM, Konrad Dybcio wrote:
On 23.08.2023 12:41, Abel Vesa wrote:
On 23-08-16 19:56:46, Konrad Dybcio wrote:
On 16.08.2023 16:57, Abel Vesa wrote:
From: Jagadeesh Kona <quic_jkona@xxxxxxxxxxx>
The current HW_CTRL flag switches the video GDSC to HW control mode as
part of GDSC enable itself, instead of that use HW_CTRL_TRIGGER flag to
give consumer drivers more control and switch the GDSC mode as and when
required.
HW_CTRL_TRIGGER flag allows consumer drivers to switch the video GDSC to
HW/SW control modes at runtime using dev_pm_genpd_set_hwmode API.
Signed-off-by: Jagadeesh Kona <quic_jkona@xxxxxxxxxxx>
Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
---
Do we have any use for the HW_CTRL flag?
Perhaps it should be renamed to HW_CTRL_ALWAYS?
Or even better, *if and only if* that is necessary, add a common
property like "always_hw_managed" to the genpd code?
The HW_CTRL flag is still needed for the consumers that expect the GDSC
to be have the HW control bit set right after it gets enabled.
Guess the correct question here would be.. Are there any?
Yes, Display GDSC(mdss_gdsc) is required to be controlled always in HW control mode when it is enabled.
Oh really?
Looking at msm-5.10 techpack, only the SDE RSC driver seems to
trigger regulator fast mode (so, enabling gdsc hw_ctrl on downstream).
Yes, on downstream, display GDSC has only one consumer(SDE RSC driver) and there are no other consumers. SDE RSC driver switches the GDSC to hw control mode once GDSC is enabled and leaves it in hw control mode. Thanks!
Sorry for pulling your tongue here a bit, but would it only concern
RPMh SoCs? Designs like SM6115 don't implement RSCs, should they not
have HW_CTRL enabled at all times?
Yes, for RPMh SoCs which have display RSC block, GDSC is switched to HW control mode. For SoCs which doesn't have display RSC block, display driver controls the GDSC in SW mode on downstream. Thanks!
Thanks for explaining!
One last question, I promise.. Should we switch the MDSS GDSC to
HW_CTRL mode only after we start controlling the DISP RSC from Linux,
or should it be done regardless (because of the RPMh solving algos)?
From GDSC driver, MDSS GDSC can be switched to HW_CTRL mode regardless.
Thanks!
Regards,
Jagadeesh
Konrad
