On 07/09/2023 07:21, Varadarajan Narayanan wrote:
> IPQ53xx have different OPPs available for the CPU based on
> SoC variant. This can be determined through use of an eFuse
> register present in the silicon.
>
> Add support to read the eFuse and populate the OPPs based on it.
>
> Signed-off-by: Kathiravan T <quic_kathirav@xxxxxxxxxxx>
> };
> @@ -150,6 +173,11 @@
> reg = <0x000a4000 0x721>;
> #address-cells = <1>;
> #size-cells = <1>;
> +
> + cpu_speed_bin: cpu_speed_bin@1d {
No underscores in node names. I am pretty sure I repeated it multiple
times already...
Best regards,
Krzysztof
