On 8/10/2023 1:29 AM, Konrad Dybcio wrote:
On 8.08.2023 07:14, Imran Shaik wrote:
From: Taniya Das <quic_tdas@xxxxxxxxxxx>
Clock CBCRs with memories need an update for memory before enable/disable
of the clock. Add support for the mem ops to handle this sequence.
Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
Signed-off-by: Imran Shaik <quic_imrashai@xxxxxxxxxxx>
---
drivers/clk/qcom/clk-branch.c | 38 +++++++++++++++++++++++++++++++++++
drivers/clk/qcom/clk-branch.h | 4 ++++
2 files changed, 42 insertions(+)
diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c
index fc4735f74f0f..95ffcd380039 100644
--- a/drivers/clk/qcom/clk-branch.c
+++ b/drivers/clk/qcom/clk-branch.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/kernel.h>
@@ -134,6 +135,43 @@ static void clk_branch2_disable(struct clk_hw *hw)
clk_branch_toggle(hw, false, clk_branch2_check_halt);
}
+static int clk_branch2_mem_enable(struct clk_hw *hw)
+{
+ struct clk_branch *br = to_clk_branch(hw);
+ u32 val;
+ int count = 200;
+
+ regmap_update_bits(br->clkr.regmap, br->mem_enable_reg,
+ br->mem_enable_ack_bit, br->mem_enable_ack_bit);
+
+ regmap_read(br->clkr.regmap, br->mem_ack_reg, &val);
+
+ while (count-- > 0) {
+ if (val & br->mem_enable_ack_bit)
One more comment, since the variable is named "ack bit", perhaps the
value within could be a bit number and you could use BIT() here.
Otherwise with you having chosen u8 for the type, there's not a whole
lot of flexibility.
Sure, will check and update accordingly in next series.
Thanks,
Imran
Konrad
