On 12/07/2023 00:34, Konrad Dybcio wrote:
On 9.07.2023 06:19, Dmitry Baryshkov wrote:
Declare the displayport controller present on the Qualcomm SM8250 SoC.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
[...]
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
19.2 MHz, VDD_MIN
I don't think so, the lowest working point is 162 MHz for RBR. 19.2 is
just just artificial. I'll check, maybe it would be better to drop this
completely.
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
270 MHz, LOW_SVS
Ack. Which probably means that we should fix all existing DP opp tables.
They all should be using low_svs here.
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
540 MHz, SVS_L1 (ok)
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
810 MHz, NOM (also ok)
(but then - there's qcom,max-pclk-frequency-khz = <675000>;)
also, what's up with the PIXEL1 clocks etc.?
they are capped at the aforementioned 675 Mhz but I have no idea
what they're for
I think PIXEL1 is used for DP MST.
Konrad
+ };
+ };
+ };
+
mdss_dsi0: dsi@ae94000 {
compatible = "qcom,sm8250-dsi-ctrl",
"qcom,mdss-dsi-ctrl";
--
With best wishes
Dmitry
