Some clocks are physically part of a clock controller block (e.g. GCC),
but are under no circumstances supposed to be touched from HLOS/APSS, as
another subsystem manages them, and trying to alter its configuration
may (and likely will) wreck total havoc over whatever the clock is
attached to.
Add read-only ops for RCG clocks. This allows us to peak at the rates
(and other configuration parameters) of such clocks without the risk
of messing up half of the SoC due to an erroneous CCF call.
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
---
drivers/clk/qcom/clk-rcg.h | 1 +
drivers/clk/qcom/clk-rcg2.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index e6d84c8c7989..4b4ff156539f 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -170,6 +170,7 @@ struct clk_rcg2_gfx3d {
extern const struct clk_ops clk_rcg2_ops;
extern const struct clk_ops clk_rcg2_floor_ops;
extern const struct clk_ops clk_rcg2_mux_closest_ops;
+extern const struct clk_ops clk_rcg2_ro_ops;
extern const struct clk_ops clk_edp_pixel_ops;
extern const struct clk_ops clk_byte_ops;
extern const struct clk_ops clk_byte2_ops;
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index e22baf3a7112..71de1cd8d45b 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -518,6 +518,14 @@ const struct clk_ops clk_rcg2_mux_closest_ops = {
};
EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
+const struct clk_ops clk_rcg2_ro_ops = {
+ .is_enabled = clk_rcg2_is_enabled,
+ .get_parent = clk_rcg2_get_parent,
+ .recalc_rate = clk_rcg2_recalc_rate,
+ .get_duty_cycle = clk_rcg2_get_duty_cycle,
+};
+EXPORT_SYMBOL_GPL(clk_rcg2_ro_ops);
+
struct frac_entry {
int num;
int den;
--
2.41.0
