On 30/05/2023 17:09, Caleb Connolly wrote:
On 21/05/2023 20:36, Dmitry Baryshkov wrote:
The first USB PHY on the sm8150 platform is really the USB+DP combo
PHY. Add the DP part of the PHY.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 2273fa571988..1f442e1be63a 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3399,20 +3399,19 @@ usb_2_hsphy: phy@88e3000 {
};
usb_1_qmpphy: phy@88e9000 {
- compatible = "qcom,sm8150-qmp-usb3-phy";
+ compatible = "qcom,sm8150-qmp-usb3-dp-phy";
Subnodes need to be renamed to usb3-phy and dp-phy respectively,
otherwise this fails to probe for me.
Thanks for the test! I'll fix it in v3.
With that, for the series:
Tested-by: Caleb Connolly <caleb.connolly@xxxxxxxxxx>
reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x10>;
+ <0 0x088e8000 0 0x38>,
+ <0 0x088ea000 0 0x40>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
-
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_CLKREF_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "ref_clk_src", "ref", "com_aux";
-
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
@@ -3430,6 +3429,16 @@ usb_1_ssphy: phy@88e9200 {
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
+
+ usb_1_dpphy: phy@88ea200 {
+ reg = <0 0x088ea200 0 0x200>,
+ <0 0x088ea400 0 0x200>,
+ <0 0x088eaa00 0 0x200>,
+ <0 0x088ea600 0 0x200>,
+ <0 0x088ea800 0 0x200>;
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+ };
};
usb_2_qmpphy: phy@88eb000 {
--
With best wishes
Dmitry
