On 16/05/2023 18:39, Dmitry Baryshkov wrote:
> On Tue, 16 May 2023 at 16:30, Krzysztof Kozlowski
> <krzysztof.kozlowski@xxxxxxxxxx> wrote:
>>
>> Add PCIe0 nodes used with WCN7851 device. The PCIe1 is not connected,
>> thus skip pcie_1_phy_aux_clk input clock to GCC.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
>> ---
>> arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 32 +++++++++++++++++++++++++
>> 1 file changed, 32 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
>> index ccc58e6b45bd..e7a2bc5d788b 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
>> +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts
>> @@ -385,6 +385,38 @@ vreg_l3g_1p2: ldo3 {
>> };
>> };
>>
>> +&gcc {
>> + clocks = <&bi_tcxo_div2>, <&sleep_clk>,
>> + <&pcie0_phy>,
>> + <&pcie1_phy>,
>> + <0>,
>> + <&ufs_mem_phy 0>,
>> + <&ufs_mem_phy 1>,
>> + <&ufs_mem_phy 2>,
>> + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>> +};
>
> Is there any reason to disable the PCIe1 PHY AUX clock here? I mean,
> the PCIe1 is still enabled in the hardware.
I was thinking about this. The AUX clock seems to be an external clock,
although I could not find it in schematics. I assume that on QRD8550 it
could be missing, if it is really external. OTOH, downstream DTS did not
seem to care...
Best regards,
Krzysztof
