Add node to support the QUP5 SPI controller inside of IPQ8074.
Some devices use this bus in order to manage external switches.
Signed-off-by: Robert Marko <robimarko@xxxxxxxxx>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 64c2a30d9c25..4a682e3442f8 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -774,6 +774,20 @@ blsp1_i2c5: i2c@78b9000 {
status = "disabled";
};
+ blsp1_spi5: spi@78b9000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x78b9000 0x600>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp_dma 20>, <&blsp_dma 21>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
blsp1_i2c6: i2c@78ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
#address-cells = <1>;
--
2.40.0
