On 8.04.2023 15:48, Krzysztof Kozlowski wrote:
> The GCC clock controller needs CX power domain, at least according to
> DTS:
>
> sc7280-herobrine-crd-pro.dtb: clock-controller@100000: Unevaluated properties are not allowed ('power-domains' was unexpected)
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> ---
+CC Rajendra
Same question as with 7180
Konrad
> .../devicetree/bindings/clock/qcom,gcc-sc7280.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> index 947b47168cec..ff0b18bbb0fc 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> @@ -43,6 +43,10 @@ properties:
> - const: ufs_phy_tx_symbol_0_clk
> - const: usb3_phy_wrapper_gcc_usb30_pipe_clk
>
> + power-domains:
> + items:
> + - description: CX domain
> +
> required:
> - compatible
> - clocks
> @@ -56,6 +60,8 @@ unevaluatedProperties: false
> examples:
> - |
> #include <dt-bindings/clock/qcom,rpmh.h>
> + #include <dt-bindings/power/qcom-rpmpd.h>
> +
> clock-controller@100000 {
> compatible = "qcom,gcc-sc7280";
> reg = <0x00100000 0x1f0000>;
> @@ -71,6 +77,7 @@ examples:
> "pcie_1_pipe_clk", "ufs_phy_rx_symbol_0_clk",
> "ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
> "usb3_phy_wrapper_gcc_usb30_pipe_clk";
> + power-domains = <&rpmhpd SC7280_CX>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> #power-domain-cells = <1>;
