On 31.03.2023 16:59, Manivannan Sadhasivam wrote:
> The reset and wake properties in the PCIe EP node belong to the board dts
> as they can be customized per board design. So let's move them from SoC
> dtsi.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
On a note, is PCIe not connected to anything on the SDX55 MTP?
Konrad
> arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts | 3 +++
> arch/arm/boot/dts/qcom-sdx55.dtsi | 2 --
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
> index 81f33eba39e5..b73b707342af 100644
> --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
> +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts
> @@ -255,6 +255,9 @@ &pcie_ep {
> pinctrl-names = "default";
> pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default
> &pcie_ep_wake_default>;
> +
> + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
> };
>
> &qpic_bam {
> diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
> index 286fa92da428..bc310ed01b40 100644
> --- a/arch/arm/boot/dts/qcom-sdx55.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
> @@ -421,8 +421,6 @@ pcie_ep: pcie-ep@1c00000 {
> <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "global",
> "doorbell";
> - reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
> resets = <&gcc GCC_PCIE_BCR>;
> reset-names = "core";
> power-domains = <&gcc PCIE_GDSC>;
