On Mon, Mar 13, 2023 at 9:54 AM Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> wrote: > > > > On 24.02.2023 16:04, Jonathan Marek wrote: > > This won't work because a2xx freedreno userspace expects to own all the perfcounters. > > > > This will break perfcounters for userspace, and when userspace isn't using perfcounters, this won't count correctly because userspace writes 0 to CP_PERFMON_CNTL at the start of every submit. > > Rob, would you be willing to take this without the a2xx bits? It > should still be fine, except without devfreq. Not that we had > any significant sort of scaling on a2xx before. Yup, sounds like a plan BR, -R > Konrad > > > > On 2/23/23 5:52 AM, Konrad Dybcio wrote: > >> Implement gpu_busy based on the downstream msm-3.4 code [1]. This > >> allows us to use devfreq on this old old old hardware! > >> > >> [1] https://github.com/LineageOS/android_kernel_sony_apq8064/blob/lineage-16.0/drivers/gpu/msm/adreno_a2xx.c#L1975 > >> > >> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > >> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> > >> --- > >> drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 26 ++++++++++++++++++++++++++ > >> 1 file changed, 26 insertions(+) > >> > >> diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c > >> index c67089a7ebc1..104bdf28cdaf 100644 > >> --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c > >> +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c > >> @@ -481,6 +481,31 @@ a2xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev) > >> return aspace; > >> } > >> +/* While the precise size of this field is unknown, it holds at least these three values.. */ > >> +static u64 a2xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate) > >> +{ > >> + u64 busy_cycles; > >> + > >> + /* Freeze the counter */ > >> + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, PERF_STATE_FREEZE); > >> + > >> + busy_cycles = gpu_read64(gpu, REG_A2XX_RBBM_PERFCOUNTER1_LO); > >> + > >> + /* Reset the counter */ > >> + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, PERF_STATE_RESET); > >> + > >> + /* Re-enable the performance monitors */ > >> + gpu_rmw(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, > >> + A2XX_RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE, > >> + A2XX_RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE); > >> + gpu_write(gpu, REG_A2XX_RBBM_PERFCOUNTER1_SELECT, 1); > >> + gpu_write(gpu, REG_A2XX_CP_PERFMON_CNTL, PERF_STATE_ENABLE); > >> + > >> + *out_sample_rate = clk_get_rate(gpu->core_clk); > >> + > >> + return busy_cycles; > >> +} > >> + > >> static u32 a2xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) > >> { > >> ring->memptrs->rptr = gpu_read(gpu, REG_AXXX_CP_RB_RPTR); > >> @@ -502,6 +527,7 @@ static const struct adreno_gpu_funcs funcs = { > >> #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) > >> .show = adreno_show, > >> #endif > >> + .gpu_busy = a2xx_gpu_busy, > >> .gpu_state_get = a2xx_gpu_state_get, > >> .gpu_state_put = adreno_gpu_state_put, > >> .create_address_space = a2xx_create_address_space, > >>
