v2 -> v3: - Add [2/7], x-ref with https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21484 - De-magic-ify the remaining BIT(6) in a2xx_busy (thanks Dmitry) - Drop unnecessary else{} level in [3/7] - Pick up tags v2: https://lore.kernel.org/linux-arm-msm/20230223-topic-opp-v2-0-24ed24cd7358@xxxxxxxxxx/ v1 -> v2: - Move a2xx #defines to XML - Use dev_pm_opp_find_freq_floor in the common path in [2/6] - Clarify a comment in [2/6] - Move voting from a5xx to Adreno-wide [6/6] - Pick up tags v1: https://lore.kernel.org/linux-arm-msm/20230222-konrad-longbois-next-v1-0-01021425781b@xxxxxxxxxx This series is a combination of [1] and a subset of [2] and some new stuff. With it, devfreq is used on all a2xx-a6xx (including gmu and gmu-wrapper) and all clk_set_rate(core clock) calls are dropped in favour of dev_pm_opp_set_rate, which - drumroll - lets us scale the voltage domain. DT patches making use of that will be sent separately. On top of that, a5xx gets a call to enable icc scaling from the OPP tables. No SoCs implementing a2xx have icc support yet and a3/4xx SoCs have separate logic for that, which will be updated at a later time. Getting this in for 6.4 early would be appreciated, as that would allow for getting GMU wrapper GPUs up (without VDD&icc scaling they can only run at lower freqs, which is.. ehhh..) Changes: - a3xx busy: use the _1 counter as per msm-3.x instead of _0 - a6xx-series-opp: basically rewrite, ensure compat with all gens - a2/4xx busy: new patch - a5xx icc: new patch [1] https://lore.kernel.org/linux-arm-msm/20230130093809.2079314-1-konrad.dybcio@xxxxxxxxxx/ [2] https://lore.kernel.org/linux-arm-msm/20230214173145.2482651-1-konrad.dybcio@xxxxxxxxxx/ Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> --- Konrad Dybcio (7): drm/msm/a2xx: Include perf counter reg values in XML drm/msm/a2xx: Add REG_A2XX_RBBM_PM_OVERRIDE2 to XML drm/msm/adreno: Use OPP for every GPU generation drm/msm/a2xx: Implement .gpu_busy drm/msm/a3xx: Implement .gpu_busy drm/msm/a4xx: Implement .gpu_busy drm/msm/adreno: Enable optional icc voting from OPP tables drivers/gpu/drm/msm/adreno/a2xx.xml.h | 18 ++++++ drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 26 ++++++++ drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 11 ++++ drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 11 ++++ drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 99 +++++++++++++----------------- drivers/gpu/drm/msm/msm_gpu.c | 4 +- drivers/gpu/drm/msm/msm_gpu_devfreq.c | 2 +- 8 files changed, 117 insertions(+), 58 deletions(-) --- base-commit: aaf70d5ad5e2b06a8050c51e278b0c3a14fabef5 change-id: 20230223-topic-opp-01e7112b867d Best regards, -- Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
