Describe the bus topology for PCIe domain 6 and add the ath11k calibration variant so that the board file (calibration data) can be loaded. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216036 Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx> --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 90a5df9c7a24..5dfda12f669b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -579,6 +579,23 @@ &pcie4 { pinctrl-0 = <&pcie4_default>; status = "okay"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + bus-range = <0x01 0xff>; + + wifi@0 { + compatible = "pci17cb,1103"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + + qcom,ath11k-calibration-variant = "LE_X13S"; + }; + }; }; &pcie4_phy { -- 2.39.2
