On Tue, Feb 28, 2023, at 17:47, Manivannan Sadhasivam wrote:
> Hi,
>
> This series fixes the issue with PCI I/O ranges defined in devicetree of
> Qualcomm SoCs as reported by Arnd [1]. Most of the Qualcomm SoCs define
> identical mapping for the PCI I/O range. But the PCI device I/O ports
> are usually located between 0x0 to 64KiB/1MiB. So the defined PCI addresses are
> mostly bogus. The lack of bug report on this issue indicates that no one really
> tested legacy PCI devices with these SoCs.
>
> This series also contains a couple of cleanup patches that aligns the entries of
> ranges property.
Looks good to me. I already commented that we may also want to use
64KB everywhere instead of 1MB for the per-host window size. Regardless
of that, please add
Reviewed-by: Arnd Bergmann <arnd@xxxxxxxx>
I would also prefer to do this in fewer patches, maybe one to
change all the prefixes, and another one to change the location,
or whichever way Bjorn prefers.
Arnd
