In some very very very very unfortunate cases, the correct offset of
the QoS registers will be.. negative. One such case is MSM8998, where
The DDR BWMON occupies what-would-be-the-BIMC-base which we usually
take into account with the register calculation, making the actual
BIMC node start at what-would-be-the-BIMC-base+0x300.
In order to keep the calculation code sane, the simplest - however
ugly it may be - solution is to allow the offset to be negative.
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
---
drivers/interconnect/qcom/icc-rpm.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/interconnect/qcom/icc-rpm.h b/drivers/interconnect/qcom/icc-rpm.h
index 77e263b93c27..5e4215f25c2e 100644
--- a/drivers/interconnect/qcom/icc-rpm.h
+++ b/drivers/interconnect/qcom/icc-rpm.h
@@ -39,7 +39,7 @@ struct qcom_icc_provider {
int num_intf_clks;
enum qcom_icc_type type;
struct regmap *regmap;
- unsigned int qos_offset;
+ int qos_offset;
u64 bus_clk_rate[2];
bool keep_alive;
struct clk_bulk_data bus_clks[2];
@@ -105,7 +105,7 @@ struct qcom_icc_desc {
bool keep_alive;
enum qcom_icc_type type;
const struct regmap_config *regmap_cfg;
- unsigned int qos_offset;
+ int qos_offset;
};
/* Valid for all bus types */
--
2.39.1
