On 2/14/2023 6:33 PM, Manivannan Sadhasivam wrote:
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On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote:
This series attempts to fix the issue with core register (Ex:- DBI) accesses
causing system hang issues in platforms where there is a dependency on the
availability of PCIe Reference clock from the host for their core
initialization.
This series is verified on Tegra194 & Tegra234 platforms.
Manivannan, could you please verify on qcom platforms?
Vidya, any plan to respin this series? The EPC rework series is now merged for
v6.3.
Yes. I'll send an updated series soon.
Currently, I'm observing some regression with linux-next on Tegra
platform for endpoint mode. I'll post the patches as soon as that is
resolved.
Thanks,
Vidya Sagar
Thanks,
Mani
V5:
* Addressed review comments from Bjorn
* Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
* Skipped memory allocation if done already. This is to avoid freeing and then
allocating again during PERST# toggles from the host.
V4:
* Addressed review comments from Bjorn and Manivannan
* Added .ep_init_late() ops
* Added patches to refactor code in qcom and tegra platforms
Vidya Sagar (3):
PCI: designware-ep: Fix DBI access before core init
PCI: qcom-ep: Refactor EP initialization completion
PCI: tegra194: Refactor EP initialization completion
.../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
drivers/pci/controller/dwc/pcie-designware.h | 10 +-
drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
4 files changed, 97 insertions(+), 69 deletions(-)
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2.17.1
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