This series attempts to fix the issue with core register (Ex:- DBI) accesses causing system hang issues in platforms where there is a dependency on the availability of PCIe Reference clock from the host for their core initialization. This series is verified on Tegra194 & Tegra234 platforms. Manivannan, could you please verify on qcom platforms? V5: * Addressed review comments from Bjorn * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late() * Skipped memory allocation if done already. This is to avoid freeing and then allocating again during PERST# toggles from the host. V4: * Addressed review comments from Bjorn and Manivannan * Added .ep_init_late() ops * Added patches to refactor code in qcom and tegra platforms Vidya Sagar (3): PCI: designware-ep: Fix DBI access before core init PCI: qcom-ep: Refactor EP initialization completion PCI: tegra194: Refactor EP initialization completion .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++------- drivers/pci/controller/dwc/pcie-designware.h | 10 +- drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++-- drivers/pci/controller/dwc/pcie-tegra194.c | 4 +- 4 files changed, 97 insertions(+), 69 deletions(-) -- 2.17.1
