On 26/01/2023 16:32, Bryan O'Donoghue wrote:
The only input clock to GCC is XO or buffered CXO if routed through the
PMIC.
You can select via GCC::RCGR where dsiX_phy_pll_out_byteclk is *sourced*
from XO, GPLL0_AUX or P_DSI0_PHYPLL_BYTE.
So, obvs the byte clock can be any one of those input sources.
But the question is, if you select dsi0_phy_pll_out_byteclk - what
provides it ?
Reviewing the LK bootloader for 3.18, it *looks* to me like the dsi0 pll
is always switched on. The downstream kernel tree doesn't represent that.
0x01A9811C MDSS_DSI_0_CLK_CTRL
Type: RW
Reset State: 0x00000000 -> BIT(4) -> Turns on/off BYTECLK for the DSI.
If set to 1, clock is ON.
Hmm. I think actually it must be the case that DSI1 is a slave of DSI0.
* If and only if you set P_DSI0_PHYPLL_BYTE::SRC_SEL = 0x01, using
SRC_SEL = 0 (XO) or SRC_SEL = 0x02 (GPLL0_AUX) should negate the dependency.
I'll review downstream further - perhaps DSI1 in practice doesn't set
P_DSI0_PHYPLL_BYTE as the source clock..
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bod
