Change PLL programming to let both power and performance cluster clocks
to start from the maximum common frequency.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
drivers/clk/qcom/clk-cpu-8996.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
index ed8cb558e1aa..d51965fda56d 100644
--- a/drivers/clk/qcom/clk-cpu-8996.c
+++ b/drivers/clk/qcom/clk-cpu-8996.c
@@ -102,7 +102,7 @@ static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = {
/* PLLs */
static const struct alpha_pll_config hfpll_config = {
- .l = 60,
+ .l = 54,
.config_ctl_val = 0x200d4828,
.config_ctl_hi_val = 0x006,
.test_ctl_val = 0x1c000000,
--
2.30.2
