Allow specifying the exact calibration mode and calibration data as nvmem
cells, rather than specifying just a single calibration data blob.
Note, unlike the vendor kernel the calibration data uses hw_ids rather
than software sensor indices (to match actual tsens usage in
thermal zones).
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
.../bindings/thermal/qcom-tsens.yaml | 95 +++++++++++++++++--
1 file changed, 85 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
index f3660af0b3bf..4bb689f4602d 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -81,18 +81,63 @@ properties:
maxItems: 2
nvmem-cells:
- minItems: 1
- maxItems: 2
- description:
- Reference to an nvmem node for the calibration data
+ oneOf:
+ - minItems: 1
+ maxItems: 2
+ description:
+ Reference to an nvmem node for the calibration data
+ - minItems: 5
+ maxItems: 35
+ description: |
+ Reference to nvmem cells for the calibration mode, two calibration
+ bases and two cells per each sensor
nvmem-cell-names:
- minItems: 1
- items:
- - const: calib
- - enum:
- - calib_backup
- - calib_sel
+ oneOf:
+ - minItems: 1
+ items:
+ - const: calib
+ - enum:
+ - calib_backup
+ - calib_sel
+ - minItems: 5
+ items:
+ enum:
+ - mode
+ - base1
+ - base2
+ - s0_p1
+ - s0_p2
+ - s1_p1
+ - s1_p2
+ - s2_p1
+ - s2_p2
+ - s3_p1
+ - s3_p2
+ - s4_p1
+ - s4_p2
+ - s5_p1
+ - s5_p2
+ - s6_p1
+ - s6_p2
+ - s7_p1
+ - s7_p2
+ - s8_p1
+ - s8_p2
+ - s9_p1
+ - s9_p2
+ - s10_p1
+ - s10_p2
+ - s11_p1
+ - s11_p2
+ - s12_p1
+ - s12_p2
+ - s13_p1
+ - s13_p2
+ - s14_p1
+ - s14_p2
+ - s15_p1
+ - s15_p2
"#qcom,sensors":
description:
@@ -221,6 +266,36 @@ examples:
};
};
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ // Example 1 (new calbiration data: for pre v1 IP):
+ thermal-sensor@900000 {
+ compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
+ reg = <0x4a9000 0x1000>, /* TM */
+ <0x4a8000 0x1000>; /* SROT */
+
+ nvmem-cells = <&tsens_mode>,
+ <&tsens_base1>, <&tsens_base2>,
+ <&tsens_s0_p1>, <&tsens_s0_p2>,
+ <&tsens_s1_p1>, <&tsens_s1_p2>,
+ <&tsens_s2_p1>, <&tsens_s2_p2>,
+ <&tsens_s4_p1>, <&tsens_s4_p2>,
+ <&tsens_s5_p1>, <&tsens_s5_p2>;
+ nvmem-cell-names = "mode",
+ "base1", "base2",
+ "s0_p1", "s0_p2",
+ "s1_p1", "s1_p2",
+ "s2_p1", "s2_p2",
+ "s4_p1", "s4_p2",
+ "s5_p1", "s5_p2";
+
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+
+ #qcom,sensors = <5>;
+ #thermal-sensor-cells = <1>;
+ };
+
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
// Example 1 (legacy: for pre v1 IP):
--
2.39.0
