On Thu, Nov 03, 2022 at 10:23:55AM -0500, Bjorn Andersson wrote:
> On Thu, Nov 03, 2022 at 10:06:20AM +0100, Johan Hovold wrote:
> > On Wed, Nov 02, 2022 at 09:49:49PM -0500, Bjorn Andersson wrote:
> > > In line with the downstream dts, we have GCC_UFS{,_1}_CARD_CLKREF_CLK
> > > providing a reference clock to the two phys. Then GCC_UFS_REF_CLKREF_CLK
> > > feeds the UFS refclock pads (both of them), which connect to the memory
> > > device(s).
> > >
> > > In other words, GCC_UFS{,_1}_CARD_CLKREF_CLK should be "ref" in
> > > respective phy.
> > >
> > > GCC_UFS_REF_CLKREF_CLK is the clock to the devices, but as we don't
> > > represent the memory device explicitly it seems suitable to use as
> > > "ref_clk" in the ufshc nodes - which would then match the special
> > > handling of the "link clock" in the UFS driver.
> >
> > Thanks for clearing that up. Using GCC_UFS_REF_CLKREF_CLK as ref_clk for
> > the controller sounds reasonable.
> >
> > I guess the only missing piece is which "card" ref clock is used by
> > which PHY.
> >
> > The ADP dts uses:
> >
> > phy ref clock
> >
> > phy@1d87000 (UFS_PHY) GCC_UFS_CARD_CLKREF_CLK
> > phy@1da7000 (UFS_CARD) GCC_UFS_1_CARD_CLKREF_CLK
> >
>
> This matches the documentation.
Thanks for checking.
> > > All three clocks are sourced off the CXO pad, so I would like this patch
> > > to cover at least all of these. And
> > >
> > > Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver")
> > >
> > > seems to be in order for such patch.
> > >
> > >
> > > @Johan, would you mind writing a dts patch flipping the clocks around
> > > and Shazad can update this patch?
> >
> > I'll do so, but I'll wait with posting until you can confirm which
> > clkref is which.
I've know posted a patch fixing the devicetree here:
https://lore.kernel.org/lkml/20221104092045.17410-1-johan+linaro@xxxxxxxxxx/
Note that we need to get Shazad's clock driver fix in first as the UFS
controller driver expects a valid frequency for the device ref clock.
Johan
