On Fri 19 Aug 17:18 CDT 2022, Prashant Malani wrote: > On Fri, Aug 19, 2022 at 2:39 PM Bjorn Andersson > <bjorn.andersson@xxxxxxxxxx> wrote: > > > > On Fri 19 Aug 15:49 CDT 2022, Stephen Boyd wrote: > > > > > > I like 2 endpoints to represent the usb-c-connector, but that doesn't seem > > > > to be compatible (without introducing `data-lanes`, at least) with all > > > > the various > > > > combinations on the remote side, if that remote side is a DRM bridge with DP > > > > output capability (like it6505 or anx7625). > > > > That type of DRM bridge supports 1, 2 or 4 lane DP connections. > > > > > > Why can't the remote side that's a pure DP bridge (it6505) bundle > > > however many lanes it wants into one endpoint? If it's a pure DP bridge > > > we should design the bridge binding to have up to 4 endpoints, but > > > sometimes 2 or 1 and then overlay data-lanes onto that binding so that > > > we can tell the driver how to remap the lanes if it can. If the hardware > > > can't support remapping lanes then data-lanes shouldn't be in the > > > binding. > > 2 endpoints sounds fine to me. The overloading of the bridge-side endpoint > to mean different things depending on what it's connected to seemed odd to > me, but if that is acceptable for the bridge binding, then great. > > > The existing implementation provides the interfaces usb_role_switch, > > usb_typec_mux and usb_typec_switch. These works based on the concept > > that the USB Type-C controller will request the endpoints connected to > > the usb-c-connector about changes such as "switch to host mode", "switch > > to 2+2 USB/DP combo" and "switch orientation to reverse". We use this > > same operations to inform any endpoint at any port about these events > > and they all react accordingly. > > Right, but that implementation/assumption doesn't work so well when you > have 2 Type-C ports which might route to the same bridge (2 lane from each). > The other 2 lanes from the other endpoints can go to (say) a USB HUB. > Are you saying that two of your SS-lanes in connector A are connected to directly to the QMP PHY at the same time as two SS-lanes from connector B are connected to the same two pads on the QMP PHY - without any mux etc inbetween? I.e. that there are a set of pins in connector A which is directly connected to a set of pins in connector B? I was under the impression that in your hardware there's some component muxing the single DP output to one of the connectors. If so there should be no graph-link directly connecting the two usb-c-connectors and the one QMP PHY. Is this not the case? > > > > Perhaps I'm misunderstanding your suggestion, but if you start > > representing each individual lane in the SuperSpeed interface I believe > > you would have to just abandon this interface and replace it with > > something like "give me USB on port@1/endpoint@0 and port@1/endpoint@1 > > and give me DP on port@1/endpoint@2 and port@1/endpoint@3". > > I don't think that is necessary. The switch driver can register the switches ( > and it can find out which end-points map to the same usb-c-connector). > > From the port driver, the port driver just needs to tell each switch > registered for it's port that "I want > DP Pin assignment C/ DP Pin assignment D / Plain USB3.x" and the > switch driver(s) can figure out what to output on its pins (since > the Type-C binding will specify ep0 = A2-A3 (TX1), ep1 = B10-B11 , etc) > > orientation-switch can tell the switch if the signals need to be swapped around. > In a typical Qualcomm design the QMP PHY is directly connected to the usb-c-connector and as such it is the component that implements usb_typec_mux and usb_typec_switch. Regards, Bjorn > The above notwithstanding, it sounds like the 2-ep approach has more support > than 4 ep-approach, so this specific example is moot.
