Only one of the USB controllers supports SuperSpeed and have an SS PHY
wakeup interrupt.
Reorder the interrupts so that they match the updated binding which
specifically has the optional interrupt last.
Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index ef431c954ab5..1e739ba1923d 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3174,10 +3174,11 @@ usb_2: usb@8cf8800 {
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 13 IRQ_TYPE_EDGE_RISING>,
- <&pdc 12 IRQ_TYPE_EDGE_RISING>;
+ <&pdc 12 IRQ_TYPE_EDGE_RISING>,
+ <&pdc 13 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "hs_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq";
power-domains = <&gcc GCC_USB30_SEC_GDSC>;
@@ -3357,13 +3358,13 @@ usb_1: usb@a6f8800 {
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 17 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 14 IRQ_TYPE_LEVEL_HIGH>;
+ <&pdc 17 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
--
2.35.1
