Re: [PATCH v11 0/5] PCI: qcom: Rework pipe_clk/pipe_clk_src handling

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On Wed, Jun 08, 2022 at 01:52:33PM +0300, Dmitry Baryshkov wrote:
> PCIe pipe clk (and some other clocks) must be parked to the "safe"
> source (bi_tcxo) when corresponding GDSC is turned off and on again.
> Currently this is handcoded in the PCIe driver by reparenting the
> gcc_pipe_N_clk_src clock.
> 
> Instead of doing it manually, follow the approach used by
> clk_rcg2_shared_ops and implement this parking in the enable() and
> disable() clock operations for respective pipe clocks.
> 
> Changes since v10:
>  - Added linux/bitfield.h include (lkp)
>  - Split fw_name/name lines in the gcc-sm8450.c (Johan)
> 
> Changes since v9:
>  - Respin fixing Tested-by tags, no code changes
> 
> Changes since v8:
>  - Readded .name to changed entries in gcc-sc7280 driver to restore
>    compatibility with older DTS,
>  - Rebased on top of linux-next, dropping reverts,
>  - Verified to include all R-b tags (excuse me, Johan, I missed them
>    in the previous iteration).
> 
> Changes since v7:
>  - Brought back the struct clk_regmap_phy_mux (Johan)
>  - Fixed includes (Stephen)
>  - Dropped CLK_SET_RATE_PARENT flags from changed pipe clocks, they are
>    not set in the current code and they are useless as the PHY's clock
>    has fixed rate.
> 
> Changes since v6:
>  - Switched the ops to use GENMASK/FIELD_GET/FIELD_PUT (Stephen),
>  - As all pipe/symbol clock source clocks have the same register (and
>    parents) layout, hardcode all the values. If the need arises, this
>    can be changed later (Stephen),
>  - Fixed commit messages and comments (suggested by Johan),
>  - Added revert for the clk_regmap_mux_safe that have been already
>    picked up by Bjorn.
> 
> Changes since v5:
>  - Rename the clock to clk-regmap-phy-mux and the enable/disable values
>    to phy_src_val and ref_src_val respectively (as recommended by
>    Johan).
> 
> Changes since v4:
>  - Renamed the clock to clk-regmap-pipe-src,
>  - Added mention of PCIe2 PHY to the commit message,
>  - Expanded commit messages to mention additional pipe clock details.
> 
> Changes since v3:
>  - Replaced the clock multiplexer implementation with branch-like clock.
> 
> Changes since v2:
>  - Added is_enabled() callback
>  - Added default parent to the pipe clock configuration
> 
> Changes since v1:
>  - Rebased on top of [1].
>  - Removed erroneous Fixes tag from the patch 4.
> 
> Changes since RFC:
>  - Rework clk-regmap-mux fields. Specify safe parent as P_* value rather
>    than specifying the register value directly
>  - Expand commit message to the first patch to specially mention that
>    it is required only on newer generations of Qualcomm chipsets.
> 
> Dmitry Baryshkov (5):
>   clk: qcom: regmap: add PHY clock source implementation
>   clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe
>     clocks
>   clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe
>     clocks
>   PCI: qcom: Remove unnecessary pipe_clk handling
>   PCI: qcom: Drop manual pipe_clk_src handling
> 
> 
> Dmitry Baryshkov (5):
>   clk: qcom: regmap: add PHY clock source implementation
>   clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe
>     clocks
>   clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe
>     clocks
>   PCI: qcom: Remove unnecessary pipe_clk handling
>   PCI: qcom: Drop manual pipe_clk_src handling
> 
>  drivers/clk/qcom/Makefile              |  1 +
>  drivers/clk/qcom/clk-regmap-phy-mux.c  | 62 ++++++++++++++++++++
>  drivers/clk/qcom/clk-regmap-phy-mux.h  | 33 +++++++++++
>  drivers/clk/qcom/gcc-sc7280.c          | 49 +++++-----------
>  drivers/clk/qcom/gcc-sm8450.c          | 49 +++++-----------
>  drivers/pci/controller/dwc/pcie-qcom.c | 81 +-------------------------
>  6 files changed, 127 insertions(+), 148 deletions(-)
>  create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.c
>  create mode 100644 drivers/clk/qcom/clk-regmap-phy-mux.h

I applied this to pci/ctrl/qcom for v5.20, thanks!

Clock folks (Bjorn A, Andy, Michael, Stephen), I assume you're OK with
these being merged via the PCI tree.  Let me know if you prefer
anything different.



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