On Mon, May 02, 2022 at 08:36:11PM +0530, Manivannan Sadhasivam wrote: > If I get the logic behind this "parking" thing right, then it is required > for producing a stable pipe_clk from GCC when the PHY is about to initialize. > Also to make sure that there is no glitch observed on pipe_clk while > initializing the PHY. And once it is powered ON properly, the pipe_clksrc > should be used as the parent for pipe_clk. No, the "parking" is only needed when toggling the corresponding GDSC which needs a ticking source for some handshake or else it hangs. The PHY PLL could be muxed in whenever the GDSC power domain is enabled. That's the thing I don't like about tying the muxing to gating the pipe clock in the PHY driver. It just happens to work as long as we remember to gate before disabling the power domain (for a separate device, the PCIe controller). But that doesn't solve the case were the boot firmware has left things in a weird state. Johan
