Quoting Rohit Agarwal (2022-02-21 20:56:23) > On SDX65 there is a separate A7 PLL which is used to provide high > frequency clock to the Cortex A7 CPU via a MUX. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@xxxxxxxxxxx> > --- Reviewed-by: Stephen Boyd <sboyd@xxxxxxxxxx>
