Here are a couple fixes for the arm smmu driver. The first one deals with ensuring that we program CBn_TCR correctly when we are programming a stage-1 context bank. The second patch ensures that SMR registers are not touched when stream matchign is not supported by the hardware. When stream id matching is not supported by the hardware the SMR registers does not exists. However, even if they are UNK/SBZP we prefer not to write to more registers than needed. v1 -> v2: * Fixed so that SL0 is programed for SMMUv1 hardware also * Rebased onto Will's iommu/pci branch which only left one issue to fix for the second patch. Olav Haugan (2): iommu/arm-smmu: Fix programming of SMMU_CBn_TCR for stage 1 iommu/arm-smmu: Do not access non-existing SMR registers drivers/iommu/arm-smmu.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
