Quoting Rohit Agarwal (2022-02-15 02:02:18) > Add support for PLL found in Qualcomm SDX65 platforms which is used to > provide clock to the Cortex A7 CPU via a mux. This PLL can provide high > frequency clock to the CPU above 1GHz as compared to the other sources > like GPLL0. > > In this driver, the power domain is attached to the cpudev. This is > required for CPUFreq functionality and there seems to be no better place > to do other than this driver (no dedicated CPUFreq driver). > > Signed-off-by: Rohit Agarwal <quic_rohiagar@xxxxxxxxxxx> > --- Reviewed-by: Stephen Boyd <sboyd@xxxxxxxxxx>
