Add a driver config support for the SDX65 APCS clock controller. It is part of the APCS hardware block, which among other things implements a combined mux and half integer divider functionality. The APCS clock controller has 3 parent clocks: 1. Board XO 2. Fixed rate GPLL0 3. A7 PLL This is required for enabling CPU frequency scaling on SDX65-based platforms. Signed-off-by: Rohit Agarwal <quic_rohiagar@xxxxxxxxxxx> --- drivers/clk/qcom/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 10d75d3..05abf78 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -55,13 +55,13 @@ config QCOM_CLK_APCC_MSM8996 drivers for dynamic power management. config QCOM_CLK_APCS_SDX55 - tristate "SDX55 APCS Clock Controller" + tristate "SDX55 and SDX65 APCS Clock Controller" depends on QCOM_APCS_IPC || COMPILE_TEST help - Support for the APCS Clock Controller on SDX55 platform. The + Support for the APCS Clock Controller on SDX55, SDX65 platform. The APCS is managing the mux and divider which feeds the CPUs. Say Y if you want to support CPU frequency scaling on devices - such as SDX55. + such as SDX55, SDX65. config QCOM_CLK_RPM tristate "RPM based Clock Controller" -- 2.7.4
