On Thu, Feb 17, 2022 at 5:32 AM <michael.srba@xxxxxxxxx> wrote: > > From: Michael Srba <Michael.Srba@xxxxxxxxx> > > This patch adds bindings for the AHB bus which exposes the SCC block in > the global address space. This bus (and the SSC block itself) is present > on certain qcom SoCs. > > In typical configuration, this bus (as some of the clocks and registers > that we need to manipulate) is not accessible to the OS, and the > resources on this bus are indirectly accessed by communicating with a > hexagon CPU core residing in the SSC block. In this configuration, the > hypervisor is the one performing the bus initialization for the purposes > of bringing the haxagon CPU core out of reset. > > However, it is possible to change the configuration, in which case this > binding serves to allow the OS to initialize the bus. > > Signed-off-by: Michael Srba <Michael.Srba@xxxxxxxxx> > --- > NOTE: this applies against v5.17-rc4 just fine; dt_binding_check seems > to have an issue with indentation, but the indentation looks correct > to me as well as to local dt_binding_check; also, it seems that the > rest of this series doesn't get applied before checking for compile > errors on the example, which results in missing defines for > GCC_IM_SLEEP, AGGRE2_SNOC_NORTH_AXI, SSC_XO, and SSC_CNOC_AHBS_CLK. > > CHANGES: > - v2: fix issues caught by by dt-schema > - v3: none > - v4: address the issues pointed out in the review > - v5: clarify type of additional properties; remove ssc_tlmm node for now > - v6: none > --- > .../bindings/bus/qcom,ssc-block-bus.yaml | 143 ++++++++++++++++++ > 1 file changed, 143 insertions(+) > create mode 100644 Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml > > diff --git a/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml > new file mode 100644 > index 000000000000..4044af0afda8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/bus/qcom,ssc-block-bus.yaml > @@ -0,0 +1,143 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs > + > +maintainers: > + - Michael Srba <Michael.Srba@xxxxxxxxx> > + > +description: | > + This binding describes the dependencies (clocks, resets, power domains) which > + need to be turned on in a sequence before communication over the AHB bus > + becomes possible. > + > + Additionally, the reg property is used to pass to the driver the location of > + two sadly undocumented registers which need to be poked as part of the sequence. > + > +properties: > + compatible: > + items: > + - const: qcom,msm8998-ssc-block-bus > + - const: qcom,ssc-block-bus > + > + reg: > + description: | > + Shall contain the addresses of the SSCAON_CONFIG0 and SSCAON_CONFIG1 > + registers > + minItems: 2 > + maxItems: 2 > + > + reg-names: > + items: > + - const: mpm_sscaon_config0 > + - const: mpm_sscaon_config1 > + > + '#address-cells': > + enum: [ 1, 2 ] > + > + '#size-cells': > + enum: [ 1, 2 ] > + > + ranges: true > + > + clocks: > + minItems: 6 > + maxItems: 6 > + > + clock-names: > + items: > + - const: xo > + - const: aggre2 > + - const: gcc_im_sleep > + - const: aggre2_north > + - const: ssc_xo > + - const: ssc_ahbs > + > + power-domains: > + description: Power domain phandles for the ssc_cx and ssc_mx power domains > + minItems: 2 > + maxItems: 2 > + > + power-domain-names: > + items: > + - const: ssc_cx > + - const: ssc_mx > + > + resets: > + description: | > + Reset phandles for the ssc_reset and ssc_bcr resets (note: ssc_bcr is the > + branch control register associated with the ssc_xo and ssc_ahbs clocks) > + minItems: 2 > + maxItems: 2 > + > + reset-names: > + items: > + - const: ssc_reset > + - const: ssc_bcr > + > + qcom,halt-regs: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: describes how to locate the ssc AXI halt register > + items: > + - items: > + - description: Phandle reference to a syscon representing TCSR > + - description: offset for the ssc AXI halt register These need indenting 2 more spaces. With that, Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
