On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote: > The Krait L1/L2 error reporting hardware is made up a per-CPU > interrupt for the L1 cache and a SPI interrupt for the L2. > > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx> > Cc: Mark Rutland <mark.rutland@xxxxxxx> > Cc: Kumar Gala <galak@xxxxxxxxxxxxxx> > Cc: <devicetree@xxxxxxxxxxxxxxx> > Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/arm/cache.txt | 48 ++++++++++++++++++++++++- > 1 file changed, 47 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt > index b90fcc7c53cf..d7357e777399 100644 > --- a/Documentation/devicetree/bindings/arm/cache.txt > +++ b/Documentation/devicetree/bindings/arm/cache.txt Right, that's http://www.spinics.net/lists/arm-kernel/msg308540.html So whoever picks those patches up, Lorenzo's doc needs to be in his tree first too. How about I review the EDAC part and an arm maintainer picks the whole series up? Would that be easier, logistically? -- Regards/Gruss, Boris. Sent from a fat crate under my desk. Formatting is fine. -- -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
