Hi Marc, As part of testing ARM Generic Timer support on MSM platform with your local timers patch, ran into a behavior for which I could not find documentation in the ARM spec. http://lists.infradead.org/pipermail/linux-arm-kernel/2011-August/060489.html +static int arch_timer_set_next_event(unsigned long evt, + struct clock_event_device *unused) +{ + unsigned long ctrl; + + ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL); + ctrl |= ARCH_TIMER_CTRL_ENABLE; + ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; + + arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt); + arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); + + return 0; +} + On MSM platforms, timer interrupt is level triggered and is de-asserted when a new TVAL is written only when the interrupt is unmasked. In arch_timer_set_next_event() routine since the TVAL is written with the interrupts masked, the level triggered interrupt never gets de-asserted. - arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt); arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl); + arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt); Changing the ordering to unmask the interrupt first and then updating the TVAL as above works on MSM platform. Would you happen to know if this behavior is documented in ARM specification, if so where I could find this information. Also if there is a more recent patch, could you point me to it. Thanks Sathish -- Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
