On 12 December 2010 04:58, Saravana Kannan <skannan@xxxxxxxxxxxxxx> wrote: > As you and James suggested, having the NS bit set by the secure world is > definitely a solution that would work. But IMHO, the explicit cache > flush/invalidate approach keeps the design simple and easy to maintain. That is indeed an approach to the problem. But it depends on whether we consider the DMA API appropriate for this. We can view the secure world as a non-coherent agent accessing the memory and could try to justify the use of the DMA API in Linux. At some point we'll probably have platforms supporting cacheable DMA (e.g. via the ARM coherency port) and the DMA API would no longer give you what you need. But it is also possible that platforms with ACP would only have 1 or 2 devices on that port (some HD LCD controller for example) and the rest of devices non-coherent. In this case, we need to have different DMA operations depending on the bus/device (via get_dma_ops) and thus we can allow your scenario via dedicated DMA ops. -- Catalin -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
