On 13 December 2010 01:20, <ykaoua@xxxxxxxxxxxx> wrote: > --- /dev/null > +++ b/arch/arm/mach-msm/headsmp.S [...] > +ENTRY(msm_secondary_startup) > +    mrc   p15, 0, r0, c0, c0, 5  @ MPIDR > +    and   r0, r0, #15       @ What CPU am I > +    adr   r4, 1f         Â@ address of > +    ldmia  r4, {r5, r6}      Â@ load curr addr and pen_rel addr > +    sub   r4, r4, r5       Â@ determine virtual/phys offsets > +    add   r6, r6, r4       Â@ apply > +pen: > +    wfe > +    dsb               @ ensure subsequent access is > +                    @ after event > + > +    ldr   r7, [r6]        Â@ pen_rel has cpu to remove from reset > +    cmp   r7, r0         Â@ are we lucky? > +    bne   pen Is the primary CPU using SEV to wake the secondary from the WFE? I may have missed it. -- Catalin ÿô.nÇ·®+%˱é¥wÿº{.nÇ·¥{±ýþ)íèjg¬±¨¶Ýjÿ¾«þG«é¸¢·¦j:+v¨wèm¶ÿþø®w¥þ࣢·hâÿÙ