On 20/01/2023 15:09, Yann Sionneau wrote: > From: Jules Maselbas <jmaselbas@xxxxxxxxx> > > Add documentation for `kalray,kv3-1-apic-gic` binding. > > Co-developed-by: Jules Maselbas <jmaselbas@xxxxxxxxx> > Signed-off-by: Jules Maselbas <jmaselbas@xxxxxxxxx> > Signed-off-by: Yann Sionneau <ysionneau@xxxxxxxxx> > --- All the comments apply here and to all your other patches - wrong subject, missing blank lines, missing additionalProperties, missing tests (patches were for sure not tested as you can see from bot's answers) etc. Really, please start from scratch on example-schema. > > Notes: > V1 -> V2: new patch > > .../kalray,kv3-1-apic-gic.yaml | 66 +++++++++++++++++++ > 1 file changed, 66 insertions(+) > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-apic-gic.yaml > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-apic-gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-apic-gic.yaml > new file mode 100644 > index 000000000000..7a37f19db2fb > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/kalray,kv3-1-apic-gic.yaml > @@ -0,0 +1,66 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/kalray,kv3-1-apic-gic# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Kalray kv3-1 APIC-GIC > + > +description: | > + Each cluster in the Coolidge SoC includes an Advanced Programmable Interrupt > + Controller (APIC) which is split in two part: > + - a Generic Interrupt Controller (referred as APIC-GIC) > + - a Mailbox Controller (referred as APIC-Mailbox) > + The APIC-GIC acts as an intermediary interrupt controller, muxing/routing > + incoming interrupts to output interrupts connected to kvx cores interrupts lines. > + The 139 possible input interrupt lines are organized as follow: > + - 128 from the mailbox controller (one it per mailboxes) > + - 1 from the NoC router > + - 5 from IOMMUs > + - 1 from L2 cache DMA job FIFO > + - 1 from cluster watchdog > + - 2 for SECC, DECC > + - 1 from Data NoC > + The 72 possible output interrupt lines: > + - 68 : 4 interrupts per cores (17 cores) > + - 1 for L2 cache controller > + - 3 extra that are for padding > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + > +properties: > + compatible: > + const: kalray,kv3-1-apic-gic Missing reg > + "#interrupt-cells": > + const: 1 > + description: > + The IRQ number. > + interrupt-controller: true > + interrupt-parent: true Drop, should not be needed. > + interrupts: > + maxItems: 4 > + description: | > + Specifies the interrupt line(s) in the interrupt-parent controller node; > + valid values depend on the type of parent interrupt controller > + > +required: > + - compatible > + - reg > + - "#interrupt-cells" > + - interrupt-controller > + - interrupt-parent > + - interrupts > + > +examples: > + - | > + apic_gic: interrupt-controller@a20000 { > + compatible = "kalray,kv3-1-apic-gic"; > + reg = <0 0xa20000 0 0x12000>; > + #interrupt-cells = <1>; > + interrupt-controller; > + interrupt-parent = <&intc>; > + interrups = <4 5 6 7>; > + }; > + > +... Best regards, Krzysztof
