Hi Boqun & Andrea, On Sun, Apr 17, 2022 at 10:26 AM Boqun Feng <boqun.feng@xxxxxxxxx> wrote: > > On Sun, Apr 17, 2022 at 12:49:44AM +0800, Guo Ren wrote: > [...] > > > > If both the aq and rl bits are set, the atomic memory operation is > > sequentially consistent and cannot be observed to happen before any > > earlier memory operations or after any later memory operations in the > > same RISC-V hart and to the same address domain. > > "0: lr.w %[p], %[c]\n" > > " sub %[rc], %[p], %[o]\n" > > " bltz %[rc], 1f\n". > > - " sc.w.rl %[rc], %[rc], %[c]\n" > > + " sc.w.aqrl %[rc], %[rc], %[c]\n" > > " bnez %[rc], 0b\n" > > - " fence rw, rw\n" > > "1:\n" > > So .rl + fence rw, rw is over constraints, only using sc.w.aqrl is more proper. > > > > Can .aqrl order memory accesses before and after it (not against itself, > against each other), i.e. act as a full memory barrier? For example, can
