* Mathieu Desnoyers: > + * will ensure that the STORE to B happens after the LOAD of A. Normally a > + * control dependency relies on a conditional branch having a data dependency > + * on the LOAD and an architecture's inability to speculate STOREs. IOW, this > + * provides a LOAD->STORE order. > + * > + * Due to optimizing compilers, extra care is needed; as per the example above > + * the LOAD must be 'volatile' qualified in order to ensure the compiler > + * actually emits the load, such that the data-dependency to the conditional > + * branch can be formed. > + * > + * Secondly, the compiler must be prohibited from lifting anything out of the > + * selection statement, as this would obviously also break the ordering. > + * > + * Thirdly, architectures that allow the LOAD->STORE reorder must ensure > + * the compiler actually emits the conditional branch instruction. If you need a specific instruction emitted, you need a compiler intrinsic or inline assembly. So something like this: #define control_dep(x) \ ({ \ __typeof(x) x__ = (x); \ __asm__("test $0, %0\n\t" \ "jnz 1f\n\t" \ "1:" \ :: "r"(x__) : "cc"); \ }) with an appropriate instruction sequence for each architecture. I don't think it's possible to piggy-back this on something else. Thanks, Florian