Hi James, On 2020/3/26 0:15, James Morse wrote: > Hi Zhenyu, > > On 3/24/20 1:45 PM, Zhenyu Ye wrote: >> In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL >> feature allows TLBs to be issued with a level allowing for quicker >> invalidation. This series provide support for this feature. >> >> Patch 1 and Patch 2 was provided by Marc on his NV series[1] patches, >> which detect the TTL feature and add __tlbi_level interface. > > How does this interact with THP? > (I don't see anything on that in the series.) > > With THP, there is no one answer to the size of mapping in a VMA. > This is a problem because the arm-arm has in "Translation table level > hints" in D5.10.2 of DDI0487E.a: > | If an incorrect value for the entry being invalidated by the > | instruction is specified in the TTL field, then no entries are > | required by the architecture to be invalidated from the TLB. > > If we get it wrong, not TLB maintenance occurs! > Thanks for your review. With THP, we should update the TTL value after the page collapse and merge. If not sure what it should be, we can set it to 0 to avoid "no TLB maintenance occur" problem. The Table D5-53 in DDI0487E.a says: | when TTL[1:0] is 0b00: | This value is reserved, and hardware should treat this as if TTL[3:2] is 0b00 | when TTL[3:2] is 0b00: | Hardware must assume that the entry can be from any level. > Unless THP leaves its fingerprints on the vma, I think you can only do > this for VMA types that THP can't mess with. (see > transparent_hugepage_enabled()) > I will try to add struct mmu_gather to TLBI interfaces, which has enough info to track tlb's level. See in next patch version! Thanks, Zhenyu .
