On 06/03/2020 07:54, Arnd Bergmann wrote:
On Fri, Mar 6, 2020 at 4:44 AM Sinan Kaya <okaya@xxxxxxxxxx> wrote:
On 3/3/2020 11:40 AM, Arnd Bergmann wrote:
- ret = read##bw(PCI_IOBASE + addr);
+ __io_pbr();
+ ret = __raw_read##bw(PCI_IOBASE + addr);
+ __io_pbr();
__io_par();
Why do we need to change read##bw above?
read##bw already provides strong ordering guarantees across multiple
architectures.
The exact semantics of inl() and readl() are slightly different, so they
have distinct sets of barriers in the asm-generic/io.h implementation.
For instance, the arm64 architectures defines in_par() as '__iormb(v)',
but defines __io_ar() as a '__rmb()'. Similarly, riscv defines them
as "fence i,ior" and "fence i,r".
You could argue that the definitions are wrong (I have not checked the
history of the definitions), but as long as the inb() in asm-generic/io.h
uses those, the implementation in lib/logic_pio.c uses the same ones
to make the two behave the same way.
So the change would look like:
-- a/lib/logic_pio.c
+++ b/lib/logic_pio.c
@@ -229,13 +229,21 @@ unsigned long
logic_pio_trans_cpuaddr(resource_size_t addr)
}
#if defined(CONFIG_INDIRECT_PIO) && defined(PCI_IOBASE)
+
+#define logic_in_to_cpu_b(x) (x)
+#define logic_in_to_cpu_w(x) __le16_to_cpu(x)
+#define logic_in_to_cpu_l(x) __le32_to_cpu(x)
+
#define BUILD_LOGIC_IO(bw, type) \
type logic_in##bw(unsigned long addr) \
{ \
type ret = (type)~0; \
\
if (addr < MMIO_UPPER_LIMIT) { \
- ret = read##bw(PCI_IOBASE + addr); \
+ void __iomem *_addr = PCI_IOBASE + addr; \
+ __io_pbr(); \
+ ret = logic_in_to_cpu_##bw(__raw_read##bw(_addr)); \
+ __io_par(ret); \
} else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) {\
struct logic_pio_hwaddr *entry = find_io_rang
We could prob combine the le_to_cpu and __raw_read into a single macro.
John
