On Fri, Mar 6, 2020 at 4:44 AM Sinan Kaya <okaya@xxxxxxxxxx> wrote:
>
> On 3/3/2020 11:40 AM, Arnd Bergmann wrote:
> >> - ret = read##bw(PCI_IOBASE + addr);
> >> + __io_pbr();
> >> + ret = __raw_read##bw(PCI_IOBASE + addr);
> >> + __io_pbr();
> > __io_par();
> >
>
> Why do we need to change read##bw above?
>
> read##bw already provides strong ordering guarantees across multiple
> architectures.
The exact semantics of inl() and readl() are slightly different, so they
have distinct sets of barriers in the asm-generic/io.h implementation.
For instance, the arm64 architectures defines in_par() as '__iormb(v)',
but defines __io_ar() as a '__rmb()'. Similarly, riscv defines them
as "fence i,ior" and "fence i,r".
You could argue that the definitions are wrong (I have not checked the
history of the definitions), but as long as the inb() in asm-generic/io.h
uses those, the implementation in lib/logic_pio.c uses the same ones
to make the two behave the same way.
Arnd
