On Mon, Sep 10, 2018 at 09:16:43PM +0800, Pu Wen wrote:
> The PMU architecture for Hygon Dhyana CPU is similar to the AMD Family
> 17h one. To support Hygon Dhyana PMU, call amd_pmu_init() to share
> AMD PMU initialization flow, and change the PMU name to "HYGON".
>
> The Hygon Dhyana CPU support both legacy and extension PMC MSRs(perf
I don't know but for some reason, you are writing "Hygon Dhyana CPU" as
being plural. But it is singular:
"The Hygon Dhyna CPU supports both ..."
^
|||
> counter registers and event selection registers), so add Hygon Dhyana
> support to get bit offset in the similar way as AMD does.
"to get bit offset"?
> Signed-off-by: Pu Wen <puwen@xxxxxxxx>
> ---
> arch/x86/events/amd/core.c | 4 ++++
> arch/x86/events/amd/uncore.c | 20 +++++++++++++-------
> arch/x86/events/core.c | 4 ++++
> arch/x86/kernel/cpu/perfctr-watchdog.c | 2 ++
> 4 files changed, 23 insertions(+), 7 deletions(-)
With that addressed:
Reviewed-by: Borislav Petkov <bp@xxxxxxx>
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
