On Tue, 12 Jun 2018 16:39:55 -0700 Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx> wrote: > On Tue, Jun 12, 2018 at 4:26 PM Linus Torvalds > <torvalds@xxxxxxxxxxxxxxxxxxxx> wrote: > > > > Right. Intel depends on the current thing, ie if a page table > > *itself* is freed, we will will need to do a flush, but it's the exact > > same flush as if there had been a regular page there. > > > > That's already handled by (for example) pud_free_tlb() doing the > > __tlb_adjust_range(). > > Side note: I guess we _could_ make the "page directory" flush be > special on x86 too. > > Right now a page directory flush just counts as a range, and then a > range that is more that a few entries just means "flush everything". > > End result: in practice, every time you free a page directory, you > flush the whole TLB because it looks identical to flushing a large > range of pages. > > And in _theory_, maybe you could have just used "invalpg" with a > targeted address instead. In fact, I think a single invlpg invalidates > _all_ caches for the associated MM, but don't quote me on that. Yeah I was thinking that, you could treat it separately (similar to powerpc maybe) despite using the same instructions to invalidate it. > That said, I don't think this is a common case. But I think that *if* > you extend this to be aware of the page directory caches, and _if_ you > extend it to cover both ppc and x86, at that point all my "this isn't > generic" arguments go away. > > Because once x86 does it, it's "common enough" that it counts as > generic. It may be only a single other architecture, but it's the bulk > of all the development machines, so.. I'll do the small step first (basically just this patch as an opt-in for architectures that don't need page tables in their tlb range). But after that it would be interesting to see if x86 could do anything with explicit page table cache management. Thanks, Nick
