On Wednesday, September 15, 2010, Miklos Szeredi wrote: > Hi, > > I'm trying to understand memory barriers but not quite succeeding. > > Consider the following example: > > Start: > p = NULL; > x = 0; > > CPU1: > atomic_inc(&x); > p = &x; > > CPU2: > if (p) > z = atomic_read(p); > > Is it possible to end up with z == 0? Yes, it is. CPU1 can reorder the two instructions in theory and if the atomic_read() on CPU2 happens between them, it may return 0 in theory. > What if there's a lock/unlock before setting "p"? What if there's a write > barrier before setting "p"? A write barrier should help and locking functions are implicit memory barriers. Thanks, Rafael -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
