On Sat, 2010-04-24 at 02:45 +0100, Jamie Lokier wrote: > Catalin Marinas wrote: > > On recent ARM cores, it's only the Strongly Ordered memory that can have > > the write buffering disabled. But using such mapping for > > dma_alloc_coherent() introduces other problems like cache attribute > > aliases for a physical location (since the kernel maps the RAM as Normal > > memory already). Such aliases are not allowed hence we moved to Normal > > Non-cacheable for dma_alloc_coherent(). > > I'm surprised aliases between Normal-Cached and Normal-Uncached are ok, > while aliases between Normal-Cached and SO-Uncached are not ok. In theory, all of the aliases are banned but the Normal cacheable vs non-cacheable have been allowed in practice and current ARM implementations can cope with it (such "palliative" measures have been introduced in 2006). Other aliases aren't guaranteed to work correctly. Normal Non-cacheable memory uses the write buffer (at both the CPU and L2 cache level) while the Strongly Ordered doesn't. Normal memory accesses on the same CPU check the write buffer as well since a CPU is coherent with itself (on the D side). -- Catalin -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
