Catalin Marinas wrote: > On recent ARM cores, it's only the Strongly Ordered memory that can have > the write buffering disabled. But using such mapping for > dma_alloc_coherent() introduces other problems like cache attribute > aliases for a physical location (since the kernel maps the RAM as Normal > memory already). Such aliases are not allowed hence we moved to Normal > Non-cacheable for dma_alloc_coherent(). I'm surprised aliases between Normal-Cached and Normal-Uncached are ok, while aliases between Normal-Cached and SO-Uncached are not ok. Is it theoretically ok by the ARM specs, or just optimistic programming? :-) If optimism, it's easy to imagine an implementation where (unrequested) speculative reads populate the cached mapping, and then accesses to the Normal-Uncached alias of it get a cache hit and use that, wrongly. Or, conversely, if it definitely does not treat that as a cache hit, it's hard to imagine why SO-Uncached would be different. -- Jamie -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
