Mathieu Desnoyers <mathieu.desnoyers@xxxxxxxxxx> wrote: > Yes. Do you think the synchronization of the cycles counters is > _perfect_ across CPUs so that there is no possible way whatsoever that > two cycle counter values appear to go backward between CPUs ? (also > taking in account delays in __m_cnt_hi write-back...) Given there's currently only one CPU allowed, yes, I think it's perfect:-) It's something to re-evaluate should Panasonic decide to do SMP. > If we expect the only correct use-case to be with readl(), I don't see > the problem with added synchronization. It might be expensive if you don't actually want to call readl(). But that's on a par with using funky instructions to read the TSC, I guess. David -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
