On Fri, 7 Nov 2008, Mathieu Desnoyers wrote: > I want to make sure > > __m_cnt_hi > is read before > mmio cnt_lo read > > for the detailed reasons explained in my previous discussion with > Nicolas here : > http://lkml.org/lkml/2008/10/21/1 > > I use smp_rmb() to do this on SMP systems (hrm, actually, a rmb() could > be required so it works also on UP systems safely wrt interrupts). > > The write side is between the hardware counter, which is assumed to > increment monotonically between each read, and the value __m_cnt_hi > updated by the CPU. I don't see where we could put a wmb() there. > > Without barrier, the smp race looks as follow : > > > CPU A B > read hw cnt low (0xFFFFFFFA) > read __m_cnt_hi (0x80000000) > read hw cnt low (0x00000001) > (wrap detected : > (s32)(0x80000000 ^ 0x1) < 0) > write __m_cnt_hi = 0x00000001 > read __m_cnt_hi (0x00000001) > return 0x0000000100000001 > (wrap detected : > (s32)(0x00000001 ^ 0xFFFFFFFA) < 0) > write __m_cnt_hi = 0x80000001 > return 0x80000001FFFFFFFA > (time jumps) Could you have hardware doing such things? You would get a non cached and more expensive read on CPU B which is not in program order with the read that should have happened before, and before that second out of order read could be performed, you'd have a full sequence in program order performed on CPU A. Nicolas -- To unsubscribe from this list: send the line "unsubscribe linux-arch" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
